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INDEX PRELIMINARY
MX29F8100
FEATURES
8M-BIT [1M x 8/512K x 16] CMOS SINGLE VOLTAGE FLASH MEMORY * Page program operation
- Internal address and data latches for 128 bytes/64 words per page - Page programming time: 3ms typical - Byte programming time: 24us in average Low power dissipation - 50mA active current - 100uA standby current CMOS and TTL compatible inputs and outputs Two independently Protected sectors Deep Power-Down Current - 1uA ICC typical Industry standard surface mount packaging - 48 lead TSOP, TYPE I - 44 lead SOP
* * * * *
5V 10% write and erase JEDEC-standard EEPROM commands Endurance : 10,000 cycles Fast access time: 120/150ns Sector erase architecture - 8 equal sectors of 128k bytes each - Sector erase time: 50ms typical * Auto Erase and Auto Program Algorithms - Automatically erases any one of the sectors or the whole chip with Erase Suspend capability - Automatically programs and verifies data at specified addresses * Status Register feature for detection of program or erase cycle completion * Low VCC write inhibit < 3.2V * Software and hardware data protection
* * * * *
GENERAL DESCRIPTION
The MX29F8100 is a 8-mega bit Flash memory organized as either 512K wordx16 or 1M bytex8. The MX29F8100 includes 8-128KB(131,072) blocks or 8-64KW(65,536) blocks. MXIC's Flash memories offer the most costeffective and reliable read/write non-volatile random access memory. The MX29F8100 is packaged in 48-pin TSOP or 44-pin SOP. For 48-pin TSOP, CE2 and RY/BY are extra pins compared with 44-pin SOP package. This is to optimize the products (such as solid-state disk drives or flash memory cards) control pin budget. PWD is available in 48 -pin TSOP for low power environment. All the above three pins(CE2,RY/BY and PWD) plus one extra VCC pin are not provided in 44-pin SOP. It is designed to be reprogrammed and erased in-system or in-standard EPROM programmers. The standard MX29F8100 offers access times as fast as 100ns,allowing operation of high-speed microprocessors without wait. To eliminate bus contention, the MX29F8100 has separate chip enables(CE1 and CE2), output enable (OE), and write enable (WE) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F8100 uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.
P/N: PM0262
To allow for simple in-system reprogrammability, the MX29F8100 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. MXIC Flash technology reliably stores memory contents even after 10,000 cycles. The MXIC's cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F8100 uses a 5V 10% VCC supply to perform the Auto Erase and Auto Program algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC +1V.
1
REV.2.0, JAN. 22, 1999
INDEX
MX29F8100
PIN CONFIGURATIONS
44 SOP(500mil)
NC NC WE A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE1 GND OE Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC WP A19* A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
48 TSOP(TYPE I) (12mm x 20mm)
RY/BY A16 A15 A14 A13 A12 A11 A10 A9 A8 A19* WP WE A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PWD BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND CE1 CE2
MX29F8100
MX29F8100
(NORMAL TYPE)
PWD BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND CE1 CE2
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
MX29F8100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
RY/BY A16 A15 A14 A13 A12 A11 A10 A9 A8 A19* WP WE A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 VCC
(REVERSE TYPE) PIN DESCRIPTION
SYMBOL A0 - A18 Q0 - Q14 Q15/A - 1 CE1/CE2 PWD OE PIN NAME Address Input Data Input/Output Q15(Word mode)/LSB addr.(Byte mode) Chip Enable Input Deep Power- Down Input Output Enable Input SYMBOL WE RY/BY WP BYTE VCC GND PIN NAME Write Enable Input Ready/Busy Output Sector Write Protect Input Word/Byte Selection Input Power Supply Ground Pin
*A19 : is suggested hard-wired to GND or VCC to minimize TTL current.
P/N: PM0262 REV. 2.0, JAN. 22, 1999
2
INDEX
MX29F8100
BLOCK DIAGRAM
WE CE1/CE2 OE WP PWD BYTE CONTROL INPUT LOGIC
PROGRAM/ERASE HIGH VOLTAGE
WRITE STATE
RY/BY
MACHINE (WSM)
COMMAND INTERFACE REGISTER
X-DECODER
MX29F8100 FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE
(CIR)
ADDRESS LATCH
Q15/A-1 A0-A18
AND BUFFER
COMMAND DATA DECODER
Y-DECODER
SENSE AMPLIFIER
PGM DATA HV
COMMAND DATA LATCH
PAGE PROGRAM DATA LATCH
Q0-Q15/A-1
I/O BUFFER
P/N: PM0262
REV. 2.0, JAN. 22, 1999
3
INDEX
MX29F8100
Table1.PIN DESCRIPTIONS
SYMBOL A0 - A18 Q0 - Q7 TYPE INPUT INPUT/OUTPUT NAME AND FUNCTION ADDRESS INPUTS: for memory addresses. Addresses are internally latched during a write cycle, A19 don't care.(hard wired to VCC or GND is suggested) LOW-BYTE DATA BUS: Input data and commands during Command Interface Register(CIR) write cycles. Outputs array,status and identifier data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations. Outputs array, identifier data in the appropriate read mode; not used for status register reads. Floated when the chip is de-selected or the outputs are disabled Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB ADDRESS(BYTE = LOW) CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers, decoders and sense amplifiers. With either CE1 or CE2 high, the device is deselected and power consumption reduces to Standby level upon completion of any current program or erase operations. Both CE1,CE2 must be low to select the device. CE2 is not provided in 44-pin SOP package. All timing specifications are the same for both signals. Device selection occurs with the latter falling edge of CE1 or CE2. The first rising edge of CE1 or CE2 disables the device. POWER-DOWN: Puts the device in deep power-down mode. PWD is active low; PWD high gates normal operation. PWD also locks out erase or program operation when active low providing data protection during power transitions. OUTPUT ENABLES: Gates the device's data through the output buffers during a read cycle OE is active low. WRITE ENABLE: Controls writes to the Command Interface Register(CIR). WE is active low. READY/BUSY: Indicates the status of the internal Write State Machine(WSM). When low it indicates that the WSM is performing a erase or program operation. RY/BY high indicate that the WSM is ready for new commands, sector erase is suspended or the device is in deep power-down mode. RY/BY is always active and does not float to tristate off when the chip is deselected or data output are disabled. WRITE PROTECT: Top or Bottom sector can be protected by writing a nonvolatile protect-bit for each sector. When WP is high, all sectors can be programmed or erased regardless of the state of the protect-bits. The WP input buffer is disabled when PWD transitions low(deep power-down mode). BYTE ENABLE: BYTE Low places device in x8 mode. All data is then input or output on Q0-7 and Q8-14 float. AddressQ15/A-1 selects between the high and low byte. BYTE high places the device in x16 mode, and turns off the Q15/ A-1 input buffer. Address A0, then becomes the lowest order address. DEVICE POWER SUPPLY(5V10%) GROUND
Q8 - Q14
INPUT/OUTPUT
.Q15/A -1 CE1/CE2
INPUT/OUTPUT INPUT
PWD
INPUT
OE WE RY/BY
INPUT INPUT OPEN DRAIN OUTPUT
WP
INPUT
BYTE
INPUT
VCC GND
P/N: PM0262
REV. 2.0, JAN. 22, 1999
4
INDEX
MX29F8100
BUS OPERATION
Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
Table 2.1 Bus Operations for Word-Wide Mode (BYTE = VIH)
Mode
Read OutputDisable Standby
Notes PWD CE1 CE2 OE
1,2,7 1,6,7 1,6,7 VIH VIH VIH VIL VIL VIL VIH VIH X VIL VIL VIL VIL VIL VIH VIL VIH X VIL VIL VIL VIL VIH X
WE
VIH VIH X
A0
X X X
A1
X X X
A9
X X X
Q0-Q7
DOUT HighZ HighZ
Q8-Q14
DOUT HighZ HIghZ
Q15/A-1
DOUT HighZ HighZ
RY/BY
X X X
DeepPower-Down
1,3 4,8 4,8 1,5,6
VIL VIH VIH VIH
X VIL VIL VIH
X VIH VIH VIL
X VIL VIH X
X VIL VIL X
X VID VID X
HighZ C2H 88H DIN
HighZ 00H 00H DIN
HighZ 0B 0B DIN
VOH VOH VOH X
ManufacturerID DeviceID Write
Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL)
Mode
Read OutputDisable Standby
Notes PWD CE1 CE2 OE
1,2,7,9 1,6,7 1,6,7 VIH VIH VIH VIL VIL VIL VIH VIH X VIL VIL VIL VIL VIL VIH VIL VIH X VIL VIL VIL VIL VIH X
WE
VIH VIH X
A0
X X X
A1
X X X
A9
X X X
Q0-Q7
DOUT HighZ HighZ
Q8-Q14
HighZ HIghZ HighZ
Q15/A-1
VIL/VIH X X
RY/BY
X X X
DeepPower-Down
1,3 4,8 4,8 1,5,6
VIL VIH VIH VIH
X VIL VIL VIH
X VIH VIH VIL
X VIL VIH X
X VIL VIL X
X VID VID X
HighZ C2H 88H DIN
HIghZ HighZ HighZ HIghZ
X VIL VIL VIL/VIH
VOH VOH VOH X
ManufacturerID DeviceID Write
NOTES :
1.X can be VIH or VIL for address or control pins except for RY/BY which is either VOL orVOH. 2.RY/BY output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode, RY/BY will be at VOH if it is tied to VCC through a 1K ~ 100K resistor. When the RY/BY at VOH is independent of OE while a WSM operation is in progress. 3.PWD at GND 0.2V ensures the lowest deep power-down current. 4. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes. A0 at VIL, A1 at VIH and with appropriate sector addresses provide Sector Protect Code.(Refer to Table 4) 5. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully completed through proper command sequence. 6.While the WSM is running. RY/BY in Level-Mode stays at VOL until all operations are complete. RY/BY goes to VOH when the WSM is not busy or in erase suspend mode. 7. RY/BY may be at VOL while the WSM is busy performing various operations. For example, a status register read during a write operation. 8. VID = 11.5V- 12.5V. 9. Q15/A-1 = VIL, Q0 - Q7 =D0-D7 out . Q15/A-1 = VIH, Q0 - Q7 = D8 -D15 out.
P/N: PM0262 REV. 2.0, JAN. 22, 1999
5
INDEX
MX29F8100
WRITE OPERATIONS
Commands are written to the COMMAND INTERFACE REGISTER (CIR) using standard microprocessor write timings. The CIR serves as the interface between the microprocessor and the internal chip operation. The CIR can decipher Read Array, Read Silicon ID, Erase and Program command. In the event of a read command, the CIR simply points the read path at either the array or the silicon ID, depending on the specific read command given. For a program or erase cycle, the CIR informs the write state machine that a program or erase has been requested. During a program cycle, the write state machine will control the program sequences and the CIR will only respond to status reads. During a sector/chip erase cycle, the CIR will respond to status reads and erase suspend. After the write state machine has completed its task, it will allow the CIR to respond to its full command set. The CIR stays at read status register mode until the microprocessor issues another valid command sequence. Device operations are selected by writing commands into the CIR. Table 3 below defines 8 Mbit flash family command.
TABLE 3. COMMAND DEFINITIONS
Command Sequence Bus Write Cycles Req'd First Bus Write Cycle Second Bus Write Cycle Third Bus Write Cycle Addr Data Addr Data Addr Data Read/ Reset 4 Silicon Page/Byte ID Read Program 4 4 Chip Erase 6 Sector Erase 6 Erase Erase Read Clear Suspend Resume Status Reg. Status Reg. 3 3 4 3
5555H AAH 2AAAH 55H 5555H F0H RA RD
5555H AAH 2AAAH 55H 5555H 90H 00H/01H C2H/88H
5555H AAH 2AAAH 55H 5555H A0H PA PD
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H
5555H AAH 2AAAH 55H 5555H B0H
5555H AAH 2AAAH 55H 5555H D0H
5555H AAH 2AAAH 55H 5555H 70H X SRD
5555H AAH 2AAAH 55H 5555H 50H
Fourth Bus Addr Read/Write Cycle Data Fifth Bus Write Cycle Sixth Bus Write Cycle Addr Data Addr Data
P/N: PM0262
REV. 2.0, JAN. 22, 1999
6
INDEX
MX29F8100
COMMAND DEFINITIONS(continue Table 3.)
Command Sequence Bus Write Cycles Req'd First Bus Write Cycle Second Bus Write Cycle Third Bus Write Cycle Addr Data Addr Data Addr Data Sector Sector Protection Unprotect . 6 6 Verify Sector Protect 4 Sleep Abort
3
3
5555H AAH 2AAAH 55H 5555H 60H 5555H AAH 2AAAH 55H SA** 20H
5555H AAH 2AAAH 55H 5555H 60H 5555H AAH 2AAAH 55H SA** 40H
5555H AAH 2AAAH 55H 5555H 90H * C2H*
5555H AAH 2AAAH 55H 5555H C0H
5555H AAH 2AAAH 55H 5555H E0H
Fourth Bus Addr Read/Write Cycle Data Fifth Bus Write Cycle Sixth Bus Write Cycle Addr Data Addr Data
Notes:
1.Address bit A15 -- A18 = X = Don't care for all address commands except for Program Address(PA) and Sector Address(SA). 5555H and 2AAAH address command codes stand for Hex number starting from A0 to A14. 2. Bus operations are defined in Table 2. 3. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A16 -- A18 will uniquely select any sector. 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. SRD = Data read from status register. 5. Only Q0-Q7 command data is taken, Q8-Q15 = Don't care. * Refer to Table 4, Figure 12. ** Only the top and the bottom sectors have protect- bit feature. SA = (A18,A17,A16) = 000B or 111B is valid.
P/N: PM0262
REV. 2.0, JAN. 22, 1999
7
INDEX
MX29F8100
DEVICE OPERATION SILICON ID READ
The Silicon ID Read mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5V~12.5V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are don't cares except A0 and A1. The manufacturer and device codes may also be read via the command register, for instances when the MX29F8100 is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 3. Byte 0 (A0=VIL) represents the manfacturer's code (MXIC=C2H) and byte 1 (A0=VIH) the device identifier code (MX29F8100=88H).
To terminate the operation, it is necessary to write the read/reset command sequence into the CIR.
Table 4. MX29F8100 Silion ID Codes and Verify Sector Protect Code
Type Manufacturer Code MX29F8100 Device Code Verify Sector Protect * A18 X X A17 X X A16 X X A1 VIL A0 VIL Code(HEX) DQ7 C2H* 88H* C2H** 1 1 1 DQ6 1 0 1 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0
VIL VIH VIH VIL
Sector Address***
MX29F8100 Manufacturer Code = C2H, Device Code = 88H when BYTE = VIL MX29F8100 Manufacturer Code = 00C2H, Device Code = 0088H when BYTE = VIH ** Outputs C2H at protected sector address, 00H at unprotected scetor address. ***Only the top and the bottom sectors have protect-bit feature. Sector address = ( A18,A17,A16) =000B or 111B
P/N: PM0262
REV. 2.0, JAN. 22, 1999
8
INDEX
MX29F8100
READ/RESET COMMAND
The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the CIR contents are altered by a valid command sequence.
BYTE-WIDE LOAD/WORD-WIDE LOAD
Byte(word) loads are used to enter the 128 bytes(64 words) of a page to be programmed or the software codes for data protection. A byte load(word load) is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Either byte-wide load or word-wide load is determined(Byte = VIL or VIH is latched) on the falling edge of the WE(or CE) during the 3rd command write cycle.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. The MX29F8100 is accessed like an EPROM. When CE and OE are low and WE is high the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual line control gives designers flexibility in preventing bus contention. CE stands for the combination of CE1 and CE2 in 48-pin TSOP package. CE stands for CE1 in 44-pin SOP package. Note that the read/reset command is not valid when program or erase is in progress.
PROGRAM
Any page to be programmed should have the page in the erased state first, i.e. performing sector erase is suggested before page programming can be performed. The device is programmed on a page basis. If a byte(word) of data within a page is to be changed, data for the entire page can be loaded into the device. Any byte(word) that is not loaded during the programming of its page will be still in the erased state (i.e. FFH). Once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte(word) has been loaded into the device, successive bytes(words) are entered in the same manner. Each new byte(word) to be programmed must have its high to low transition on WE (or CE) within 30us of the low to high transition of WE (or CE) of the preceding byte(word). A6 to A18 specify the page address, i.e., the device is page-aligned on 128 bytes(64 words)boundary. The page address must be valid during each high to low transition of WE or CE. A-1 to A5 specify the byte address within the page, A0 to A5 specify the word address withih the page. The byte(word) may be loaded in any order; sequential loading is not required. If a high to low transition of CE or WE is not detected whithin 100us of the last low to high transition, the load period will end and the internal programming period will start. The Auto page program terminates when status on DQ7 is '1' at which time the device stays at read status register mode until the CIR contents are altered by a valid command sequence.(Refer to table 3,6 and Figure 1,7,8)
PAGE PROGRAM
To initiate Page program mode, a three-cycle command sequence is required. There are two " unlock" write cycles. These are followed by writing the page program command-A0H. Any attempt to write to the device without the three-cycle command sequence will not start the internal Write State Machine(WSM), no data will be written to the device. After three-cycle command sequence is given, a byte(word) load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Maximum of 128 bytes of data may be loaded into each page by the same procedure as outlined in the page program section below.
P/N: PM0262
REV. 2.0, JAN. 22, 1999
9
INDEX
MX29F8100
CHIP ERASE
Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command-80H. Two more "unlock" write cycles are then followed by the chip erase command-10H. Chip erase does not require the user to program the device prior to erase. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the status on DQ7 is "1" at which time the device stays at read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence.(Refer to table 3,6 and Figure 2,7,9) Sector erase does not require the user to program the device prior to erase. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the status on DQ7 is "1" at which time the device stays at read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence.(Refer to table 3,6 and Figure 3,4,7,9))
ERASE SUSPEND
This command only has meaning while the the WSM is executing SECTOR or CHIP erase operation, and therefore will only be responded to during SECTOR or CHIP erase operation. After this command has been executed, the CIR will initiate the WSM to suspend erase operations, and then return to Read Status Register mode. The WSM will set the DQ6 bit to a "1". Once the WSM has reached the Suspend state,the WSM will set the DQ7 bit to a "1", At this time, WSM allows the CIR to respond to the Read Array, Read Status Register, Abort and Erase Resume commands only. In this mode, the CIR will not resopnd to any other comands. The WSM will continue to run, idling in the SUSPEND state, regardless of the state of all input control pins, with the exclusion of PWD. PWD low will immediately shut down the WSM and the remainder of the chip.
Table 5. MX29F8100 Sector Address Table (Byte-Wide Mode)
A19 SA0 SA1 SA2 SA3 SA4 X X X X X 1 SA17 X A18 0 0 0 0 1 ... 1 A17 A16 0 0 1 1 0 ... 1 0 1 0 1 0 ... 1 Address Range[A18, -1] 00000H--1FFFFH 20000H--3FFFFH 40000H--5FFFFH 60000H--7FFFFH 80000H--9FFFFH ................ E0000H--FFFFFH
ERASE RESUME
This command will cause the CIR to clear the suspend state and set the DQ6 to a '0', but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions.
SECTOR ERASE
Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command-80H. Two more "unlock" write cycles are then followed by the sector erase command-30H. The sector address is latched on the falling edge of WE, while the command (data) is latched on the rising edge of WE.
P/N: PM0262
REV. 2.0, JAN. 22, 1999
10
INDEX
MX29F8100
READ STATUS REGISTER
The MXIC's 8 Mbit flash family contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. The status register may be read at any time by writing the Read Status command to the CIR. After writing this command, all subsequent read operations output data from the status register until another valid command sequence is written to the CIR. A Read Array command must be written to the CIR to return to the Read Array mode. The status register bits are output on DQ2 - DQ7(table 6) whether the device is in the byte-wide (x8) or word-wide (x16) mode for the MX29F8100. In the word-wide mode the upper byte, DQ(8:15) is set to 00H during a Read Status command. In the byte-wide mode, DQ(8:14) are tri-stated and DQ15/A-1 retains the low order address function. DQ0-DQ1 is set to 0H in either x8 or x16 mode. It should be noted that the contents of the status register are latched on the falling edge of OE or CE whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the contents of the status register change while reading the status register. CE or OE must be toggled with each subsequent status read, or the completion of a program or erase operation will not be evident. The Status Register is the interface between the microprocessor and the Write State Machine (WSM). When the WSM is active, this register will indicate the status of the WSM, and will also hold the bits indicating whether or not the WSM was successful in performing the desired operation. The WSM sets status bits four through seven and clears bits six and seven, but cannot clear status bits four and five. If Erase fail or Program fail status bit is detected, the Status Register is not cleared until the Clear Status Register command is written. The MX29F8100 automatically outputs Status Register data when read after Chip Erase, Sector Erase, Page Program or Read Status Command write cycle. The default state of the Status Register after powerup and return from deep power-down mode is (DQ7, DQ6, DQ5, DQ4) = 1000B. DQ3 = 0 or 1 depends on sector-protect status, can not be changed by Clear Status Register Command or Write State Machine. DQ2 = 0 or 1 depends on Sleep status, During Sleep mode or Abort mode DQ2 is set to "1"; DQ2 is reset to "0" by Read Array command.
CLEAR STATUS REGISTER
The Eraes fail status bit (DQ5) and Program fail status bit (DQ4) are set by the write state machine, and can only be reset by the system software. These bits can indicate various failure conditions(see Table 6). By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several pages or erasing multiple blocks in squence). The status register may then be read to determine if an error occurred during that programming or erasure series. This adds flexibility to the way the device may be programmed or erased. Additionally, once the program(erase) fail bit happens, the program (erase) operation can not be performed further. The program(erase) fail bit must be reset by system software before further page program or sector (chip) erase are attempted. To clear the status register, the Clear Status Register command is written to the CIR. Then, any other command may be issued to the CIR. Note again that before a read cycle can be initiated, a Read command must be written to the CIR to specify whether the read data is to come from the Array, Status Register or Silicon ID.
P/N: PM0262
REV. 2.0, JAN. 22, 1999
11
INDEX
MX29F8100
TABLE 6. MX29F8100 STATUS REGISTER
STATUS IN PROGRESS PROGRAM ERASE SUSPEND (NOT COMPLETE) (COMPLETE) COMPLETE PROGRAM ERASE FAIL PROGRAM ERASE AFTER CLEARING STATUS REGISTER 1,2, 6,7 1,3, 6,7 1,5, 6,7 1,5, 6,7 6,7 NOTES 1,2, 6,7 1,3, 6,7 1,4, 6,7 DQ7 0 0 0 1 1 1 1 1 1 DQ6 DQ5 DQ4 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 DQ3 DQ2 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 *
NOTES: -1. DQ7 : WRITE STATE MACHINE STATUS 1 = READY, 0 = BUSY DQ6 : ERASE SUSPEND STATUS 1 = SUSPEND, 0 = NO SUSPEND DQ5 : ERASE FAIL STATUS 1 = FAIL IN ERASE, 0 = SUCCESSFUL ERASE DQ4 : PROGRAM FAIL STATUS 1 = FAIL IN PROGRAM, 0 = SUCCESSFUL PROGRAM DQ3 : SECTOR-PROTECT STATUS 1 = SECTOR 0 OR/AND 15 PROTECTED 0 = NONE OF SECTOR PROTECTED DQ2 : SLEEP STATUS 1 = DEVICE IN SLEEP STATUS 0 = DEVICE NOT IN SLEEP STATUS DQ1 - 0 = RESERVED FOR FUTURE ENHANCEMENTS. These bits are reserved for future use ; mask them out when polling the Status Register. 2. PROGRAM STATUS is for the status during Page Programming or Sector Unprotect mode. 3. ERASE STATUS is for the status during Sector/Chip Erase or Sector Protection mode. 4. SUSPEND STATUS is for both Sector and Chip Erase mode . 5. FAIL STATUS bit(DQ4 or DQ5) is provided during Page Program or Sector/Chip Erase modes respectively. 6. DQ3 = 0 or1 depends on Sector-Protect Status. 7. DQ2 = 0 or 1 depends on whether device is in the Sleep mode or not . * Once in the Sleep mode, DQ2 is set to "1", and is reset by read array command only.-
P/N: PM0262
REV. 2.0, JAN. 22, 1999
12
INDEX
MX29F8100
HARDWARE SECTOR PROTECTION
The MX29F8100 features sector protection. This feature will disable both program and erase operations in either the top or the bottom sector (0 or 7). The sector protection feature is enabled using system software by the user(Refer to table 3). The device is shipped with both sectors unprotected. Alternatively, MXIC may protect sectors in the factory prior to shipping the device. It is also possible to unprotect the sector , same as the first five write command cycles in activating sector protection mode followed by the Unprotect Sector command - 40H, the automatic Unprotect operation begins on the rising edge of the last WE pulse in the command sequence and terminates when the Status on DQ7 is '1' at which time the device stays at the read status register mode.(Refer to table 3,6 and Figure 11,12) The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence. Either Protect or Unprotect sector mode is accomplished by keeping WP high, i.e. protect-bit status can only be changed with a valid command sequence and WP at high. When WP is high, all sectors can be programmed or erased regardless of the state of the protect-bits. Protectbit status will not be changed during chip/sector erase operations. With WP at VIL, only unprotected sectors can be programmed or erased.
SECTOR PROTECTION
To activate this mode, a six-bus cycle operation is required. There are two 'unlock' write cycles. These are followed by writing the 'set-up' command. Two more 'unlock' write cycles are then followed by the Lock Sector command - 20H. Sector address is latched on the falling edge of CE or WE of the sixth cycle of the command sequence. The automatic Lock operation begins on the rising edge of the last WE pulse in the command sequence and terminates when the Status on DQ7 is '1' at which time the device stays at the read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence (Refer to table 3,6 and Figure 10,12 ).
DEEP POWER-DOWN MODE
The MXIC's 8Mbit flash family supports a typical ICC of 1uA in deep power-down mode. One of the target markets for these devices is in protable equipment where the power consumption of the machine is of prime importance. When PWD is a logic low (GND 0.2V), all circuits are turned off and the device typically draws 1uA of ICC current. During read modes, the PWD pin going low deselects the memory and places the output drivers in a high impedance state. Recovery from the deep power-down state, requires a minimum of 700 nanoseconds to access valid data. During erase or program modes, PWD low will abort either erase or program operation. The contents of the memory are no longer valid as the data has been corrupted by the PWD function. As in the read mode above, all internal circuitry is turned off to achieve the 1uA current level. PWD transitions to VIL or turning power off to the device will clear the status register.
VERIFY SECTOR PROTECT
To verify the Protect status of the Top and the Bottom sector, operation is initiated by writing Silicon ID read command into the command register. Following the command write, a read cycle from address XXX0H retrieves the Manufacturer code of C2H. A read cycle from XXX1H returns the Device code 88H. A read cycle from appropriate address returns information as to which sectors are protected. To terminate the operation, it is necessary to write the read/reset command sequence into the CIR. (Refer to table 3,4 and Figure 12)
A few retries are required if Protect status can not be verified successfully after each operation.
SECTOR UNPROTECT
PWD pin is not provided in 44-pin SOP package.
P/N: PM0262
REV. 2.0, JAN. 22, 1999
13
INDEX
MX29F8100
SLEEP MODE
The MX29F8100 features two software controlled lowpower modes : Sleep and Abort modes. Sleep mode is allowed during any current operations except that once Suspend command is issued, Sleep command is ignored. Abort mode is excuted only during Page Program and Chip/Sector Erase mode. To activate Sleep mode, a three-bus cycle operation is required. The C0H command (Refer to table 3) puts the device in the Sleep mode. Once in the Sleep mode and with CMOS input level applied, the power of the device is reduced to deep power-down current levels. The only power consumed is diffusion leakage, transistor subthreshold conduction, input leakage, and output leakage. The Sleep command allows the device to COMPLETE current operations before going into Sleep mode. Once current operation is done, device stays at read status register mode, RY/BY returns to ready state. The status registers are not reset during sleep command. Program or erase fail bit may have been set if during program/ erase mode the device retry exceeds maximum count. During Sleep mode, the status registers, Silicon ID codes remain valid and can still be read. The Device Sleep Status bit - DQ2 will indicate that the device in the sleep mode. Writing the Read Array command wakes up the device out of sleep mode. DQ2 is reset to "0" and Device returns to standby current level. same level as in deep power-down or sleep modes. Device stays at read status register mode, RY/BY returns to ready state. During Abort mode, the status registers, Silicon ID codes remain valid and can still be read. The Device Sleep Status bit - DQ2 will indicate that the device in the sleep mode. Similar to the sleep mode, A read array command MUST be written to bring the device out of the abort state without incurring any wake up latency. Note that once device is waken up, Clear status register mode is required before a program or erase operation can be executed.
RY/BY PIN POLLING
AND
PROGRAM/ERASE
RY/BY is a full CMOS output that provides a hardware method of detecting page program and sector erase completion. It transitions to VIL after a program or erase command sequence is written to the MX29F8100, and returns to VOH when the WSM has finished executing the internal algorithm. RY/BY can be connected to the interrupt input of the system CPU or controller. It is active at all times, not tristated if the CE or OE inputs are brought to VIH. RY/ BY is also VOH when the device is in erase suspend or deep power-down modes. RY/BY pin is not provided in 44-pin SOP package.
ABORT MODE
To activate Abort mode, a three-bus cycle operation is required. The E0H command (Refer to table 3) only stops Page program or Sector /Chip erase operation currently in progress and puts the device in Sleep mode. But unlike the sleep command, the program or erase operation will not be completed. Since the data in some page/sectors is no longer valid due to an incomplete program or erase operation, the program fail (DQ4) or erase fail (DQ5)bit will be set. After the abort command is executed and with CMOS input level applied, the device current is reduced to the
DATA PROTECTION
The MX29F8100 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read Array mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise.
P/N: PM0262
REV. 2.0, JAN. 22, 1999
14
INDEX
MX29F8100
LOW VCC WRITE INHIBIT
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO(= 3.2V , typically 3.5V). If VCC < VLKO, the command register is disabled and all internal program/ erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional write when VCC is above VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 10ns (typical) on CE or WE will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL,CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one.
P/N: PM0262
REV. 2.0, JAN. 22, 1999
15
INDEX
MX29F8100
Figure 1. AUTOMATIC PAGE PROGRAM FLOW CHART
START
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data A0H Address 5555H
Write Program Data/Address
NO Loading End?
YES
Wait 100us
Read Status Register
NO SR7 = 1 ? YES
SR4 = 0 ? YES
NO
Page Program Completed
Program Error
YES
Program another page?
To Continue Other Operations, Do Clear S.R. Mode First
NO
Operation Done, Device Stays At Read S.R. Mode
Note : S.R. Stands for Status Register
P/N: PM0262
REV. 2.0, JAN. 22, 1999
16
INDEX
MX29F8100
Figure 2. AUTOMATIC CHIP ERASE FLOW CHART
START
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 80H Address 5555H
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 10H Address 5555H
Read Status Register
NO NO SR7 = 1 ? YES To Execute Suspend Mode ? YES Erase Suspend Flow (Figure 4.)
SR5 = 0 ? YES
NO
Chip Erase Completed
Erase Error
Operation Done, Device Stays at Read S.R. Mode
To Continue Other Operations, Do Clear S.R. Mode First
P/N: PM0262
REV. 2.0, JAN. 22, 1999
17
INDEX
MX29F8100
Figure 3. AUTOMATIC SECTOR ERASE FLOW CHART
START
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 80H Address 5555H
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 30H Sector Address
Read Status Register
NO NO SR7 = 1 ? YES To Execute Suspend Erase ? YES Erase Suspend Flow (Figure 4.)
SR5 = 0 ? YES
NO
Sector Erase Completed
Erase Error
Operation Done, Device Stays at Read S.R. Mode
To Continue Other Operations, Do Clear S.R. Mode First
P/N: PM0262
REV. 2.0, JAN. 22, 1999
18
INDEX
MX29F8100
Figure 4. ERASE SUSPEND/ERASE RESUME FLOW CHART
START
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data B0H Address 5555H
Read Status Register
NO SR7 = 1 ? YES
SR6 = 1 ? YES
NO
NO SR5 = 0 ? YES
Erase Suspend
Erase has completed
Erase Error
Write Data AAH Address 5555H
Operation Done, Device Stays at Read S,R, Mode
To Continue Other Operations, Do Clear S.R. Mode First
Write Data 55H Address 2AAAH
Write Data F0H Address 5555H
Read Array
NO Reading End ?
YES
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data D0H Address 5555H
Continue Erase
P/N: PM0262
REV. 2.0, JAN. 22, 1999
19
INDEX
MX29F8100
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 VALUE 0C to 70C -65C to 125C -0.5V to 7.0V -0.5V to 7.0V -0.5V to 7.0V -0.5V to 13.5V NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change.
CAPACITANCE TA = 25C, f = 1.0 MHz
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance MIN. TYP. MAX. 14 16 UNIT pF pF CONDITIONS VIN = 0V VOUT = 0V
SWITCHING TEST CIRCUITS
DEVICE UNDER TEST
1.8K ohm +5V
CL 6.2K ohm
DIODES = IN3064 OR EQUIVALENT
CL = 100 pF Including jig capacitance
SWITCHING TEST WAVEFORMS
2.4V
2.0V TEST POINTS 0.8V
0.45V
2.0V 0.8V OUTPUT
INPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are < 10ns.
P/N: PM0262
REV. 2.0, JAN. 22, 1999
20
INDEX
MX29F8100
DC CHARACTERISTICS = 0C to 70 VCC = 5V10% C,
SYMBOL IIL PARAMETER Input Load Current Output Leakage Current VCC Standby Current(CMOS) NOTES MIN. 1 TYP. MAX. UNITS uA TEST CONDITIONS VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VCC = VCC Max CE1, CE2, PWD = VCC 0.2V
10 10
50 100
ILO
1
uA
ISB1
1
uA
ISB2
VCC Standby Current(TTL)
2
4
mA
VCC = VCC Max CE1, CE2, PWD = VIH
IDP
VCC Deep Power-Down Current VCC Read Current
1
1
20
uA
PWD = GND 0.2V
ICC1
1
50
60
mA
VCC = VCC Max CMOS: CE1, CE2 = GND 0.2V BYTE = GND 0.2V or VCC 0.2V Inputs = GND 0.2V or VCC 0.2V TTL : CE1, CE2 = VIL, BYTE = VIL or VIH Inputs = VIL or VIH, f = 10MHz, IOUT = 0 mA VCC = VCC Max, CMOS: CE1, CE2 = GND 0.2V BYTE = VCC 0.2V or GND 0.2V Inputs = GND 0.2V or VCC 0.2V TTL: CE1, CE2 = VIL, BYTE = VIH or VIL Inputs = VIL or VIH, f = 5MHz, IOUT = 0mA CE1, CE2 = VIH BLock Erase Suspended Program in Progress
ICC2
VCC Read Current
1
30
35
mA
ICC3
VCC Erase Suspend Current VCC Program Current VCC Erase Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
1,2
5
10
mA
ICC4
1
30
50
mA
ICC5 VIL VIH VOL VOH
1 3 4 -0.3 2.4
30
50 0.8 VCC+0.3 0.45
mA V V V V
Erase in Progress
IOL = 2.1mA IOH = -400uA
2.4
P/N: PM0262
REV. 2.0, JAN. 22, 1999
21
INDEX
MX29F8100
DC CHARACTERISTICS = 0C to 70 VCC = 5V10%(CONTINUE P.21) C,
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, T = 25 These currents are valid for all product C. versions (package and speeds). 2. ICC3 is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICC3 and ICC1/2. 3. VIL min. = -1.0V for pulse width < 50ns. VIL min. = -2.0V for pulse width < 20ns. 4. VIH max. = VCC + 1.5V for pulse width < 20ns. If VIH is over the specified maximum value, read operation cannot be guaranteed.
AC CHARACTERISTICS READ OPERATIONS
29F8100-12 MIN. MAX. 120 120 60 0 0 120 55 700 55 0 0 150 55 800 29F8100-15 MIN. MAX. 150 150 70 55
SYMBOL tACC tCE tOE tDF tOH tBACC tBHZ tDPR
DESCRIPTIONS Address to Output Delay CE to Output Delay OE to Output Delay OE High to Output Delay Address to Output hold BYTE to Output Delay BYTE Low to Output in High Z Deep Power-Down Recovery
UNIT ns ns ns ns ns ns ns ns
CONDITIONS CE=OE=VIL OE=VIL CE=VIL CE=VIL CE=OE=VIL CE= OE=VIL CE=VIL
TEST CONDITIONS: * Input pulse levels: 0.45V/2.4V * Input rise and fall times: 10ns * Output load: 1TTL gate+100pF(Including scope and jig) * Reference levels for measuring timing: 0.8V, 2.0V
NOTE:
1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
P/N: PM0262
REV. 2.0, JAN. 22, 1999
22
INDEX
MX29F8100
Figure 5. READ TIMING WAVEFORMS
Vcc Power-up
VIH
Standby
Device and address selection
Outputs Enabled Data valid
Standby
Vcc Power-down
ADDRESSES
VIL
ADDRESSES STABLE
VIH VIL
CE (1)
VIH VIL tDF
OE
VIH
WE
VIL tCE
tOE
tOH VOH
DATA OUT
VOL
HIGH Z
Data out valid
HIGH Z
tACC
5.0V
VCC
GND
tDPR VIH
PWD
VIL
NOTE: 1.CE is defined as the latter of CE1 or CE2 going Low or the first of CE1 or CE2 going High. 2.For real world application, BYTE pin should be either static high(word mode) or static low(byte mode); dynamic switching of BYTE pin is not recommended.
P/N: PM0262
REV. 2.0, JAN. 22, 1999
23
INDEX
MX29F8100
Figure 6. BYTE TIMING WAVEFORMS
VIH
ADDRESSES
VIL
ADDRESSES STABLE
VIH VIL
CE (1)
VIH VIL tDF tBACC VIH tOE
OE
BYTE
VIL tCE tOH VOH
DATA(DQ0-DQ7)
VOL
HIGH Z
Data Output
HIGH Z Data Output
tACC tBHZ VOH
DATA(DQ8-DQ15)
VOL
HIGH Z Data Output
HIGH Z
NOTE: 1.CE is defined as the latter of CE1 or CE2 going Low or the first of CE1 or CE2 going High.
P/N: PM0262
REV. 2.0, JAN. 22, 1999
24
INDEX
MX29F8100
AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS
SYMBOL tWC tAS tAH tDS tDH tOES tCES tGHWL tCS tCH tWP tWPH tBALC tBAL tSRA tCESR tWHRL tWHRLP DESCRIPTION Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time CE Setup Time Read Recover TimeBefore Write CE Setup Time CE Hold Time Write Pulse Width Write Pulse Width High Byte(Word) Address Load Cycle Byte(Word) Address Load Time Status Register Access Time CE Setup before S.R. Read WE High to RY/BY Going Low WE High to RY/BY Going Low (in Page Program mode) PWD High Recovery to WE Going Low VCC Setup Time 29F8100-12 MIN. MAX. 120 0 50 50 10 0 0 0 0 0 50 50 0.3 100 120 100 100 100.1 30 29F8100-15 MIN. MAX. 150 0 60 60 10 0 0 0 0 0 60 50 0.3 100 150 100 100 100.1 30 ns ns ns ns us us ns ns ns us UNIT ns ns ns ns ns ns ns
tPHWL tVCS
1 2
1 2
us us
P/N: PM0262
REV. 2.0, JAN. 22, 1999
25
INDEX
MX29F8100
Figure 7. COMMAND WRITE TIMING WAVEFORMS
CE
tOES tCS
tCH
OE
tWC
WE
tGHWL
tWP tAS
tWPH
tAH
ADDRESSES
VALID
tDS
tDH
DATA (D/Q)
HIGH Z DIN
VCC
tVCS
PWD
tPHWL
NOTE: 1.BYTE pin is treated as Address pin. All timing specifications for BYTE pin are the same as those for address pin. 2.BYTE pin is sampled on the falling edge of WE or CE during the 3rd command write bus cycle; for real world application, BYTE pin should be either static high(word mode) or static low(byte mode).
P/N: PM0262
REV. 2.0, JAN. 22, 1999
26
INDEX
MX29F8100
Figure 8. AUTOMATIC PAGE PROGRAM TIMING WAVEFORMS
A0~A5 55H AAH 55H
Word offset Address Last Word offset Address
A-1 (byte mode only)
Low/High Byte Select
Last Low/High Byte Select
A6~A14
tAS
55H
tAH
2AH
55H
Page Address
A15~A18
Page Address
tWC
tBALC
tBAL
CE(1)
tWP
tWPH
WE
tCES
OE
tWHRLP
RY/BY
tDS
tDH
tSRA
DATA
tPHWL
AAH
55H
A0H
Write Data
Last Write Data
SRD
PWD
NOTE: 1.CE is defined as the latter of CE1 or CE2 going low, or the first of CE1 or CE2 going high. 2.Please refer to page 9 for detail page program operation.
P/N: PM0262
REV. 2.0, JAN. 22, 1999
27
INDEX
MX29F8100
Figure 9. AUTOMATIC SECTOR/CHIP ERASE TIMING WAVEFORMS
A0~A14
5555H
tAS tAH
2AAAH
5555H
5555H
2AAAH
*/5555H
A15
A16~A18
SA/*
tCESR
CE#
tWP
tWPH
WE
tWC
tCES
OE
tWHRL
RY/BY
tDS
tDH
tSRA
DATA
tPHWL
AAH
55H
80H
AAH
55H
30H/10H
SRD
PWD
NOTES: 1.CE# is defined as the latter of CE1 or CE2 going low, or the first of CE1 or CE2 going high. 2."*" means "don't care" in this diagram. 3."SA" means "Sector Adddress".
P/N: PM0262
REV. 2.0, JAN. 22, 1999
28
INDEX
MX29F8100
Figure 10. SECTOR PROTECTION ALGORITHM
START, PLSCNT=0
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 60H Address 5555H
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Increment PLSCNT, To Protect Sector Again
Write Data 20H, Sector Address*
Read Status Register
SR7 = 1 ? YES
NO
NO
Protect Sector Operation Terminated
PLSCNT = 25 ? NO
YES
Device Failed To Verify Protect Status ? NO Device Stays at Read S.R. Mode YES Verify Protect Status Flow (Figure 12) Data = C2H ?
YES Sector Protected,Operation Done, Device Stays at Verify Sector Protect Mode
NOTE : *Only the Top or the Bottom Sector Address is vaild in this feature. i.e. Sector Address = (A18,A17,A16) = 000B or 111B
P/N: PM0262
REV. 2.0, JAN. 22, 1999
29
INDEX
MX29F8100
Figure 11. SECTOR UNPROTECT ALGORITHM
START, PLSCNT=0
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 60H Address 5555H
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Increment PLSCNT, To Unprotect Sector Again
Write Data 40H, Sector Address*
Read Status Register
SR7 = 1 ? YES
NO
NO
Unprotect Sector Operation Terminated
PLSCNT = 25 ? NO
YES
Device Failed To Verify Protect Status ? NO Device Stays at Read S.R. Mode YES Verify Protect Status Flow (Figure 12) Data = 00H ?
YES Sector Unprotected,Operation Done, Device Stays at Verify Sector Protect Mode
NOTE : *Only the Top or the Bottom Sector Address is vaild in this feature. i.e. Sector Address = (A18,A17,A16) = 000B or 111B
P/N: PM0262
REV. 2.0, JAN. 22, 1999
30
INDEX
MX29F8100
Figure 12. VERIFY SECTOR PROTECT FLOW CHART
START
Write Data AAH, Address 5555H
Write Data 55H, Address 2AAAH
Write Data 90H, Address 5555H
Ptoect Status Read*
* 1. Protect Status: Data Outputs C2H as Protected Sector Verified Code. Data Outputs 00H as Unprotected Sector Verified Code. 2. Sepecified address will be either (A18,A17,A16,A1,A0) = (00010) or (11110), the rest of the address pins are don't care. 3. Silicon ID can be read via this Flow Chart. Refer to Table 4.
P/N: PM0262
REV. 2.0, JAN. 22, 1999
31
INDEX
MX29F8100
Figure 13. COMMAND WRITE TIMING WAVEFORMS(Alternate CE Controlled)
WE
tOES tWS
tWH
OE
tWC
CE
tGHWL
tCP tAS
tCPH
tAH
ADDRESSES
VALID
tDS
tDH
DATA (D/Q)
HIGH Z DIN
VCC
tVCS
PWD
tPHWL
NOTE: 1.BYTE pin is treated as Address pin. All timing specifications for BYTE pin are the same as those for address pin. 2.BYTE pin is sampled on the falling edge of WE or CE during the 3rd command write bus cycle; for real world application, BYTE pin should be either static high(word mode) or static low(byte mode).
P/N: PM0262
REV. 2.0, JAN. 22, 1999
32
INDEX
MX29F8100
Figure 14. AUTOMATIC PAGE PROGRAM TIMING WAVEFORM(Alternate CE Controlled)
A0~A5
55H
AAH
55H
Word offset Address
Last Word Offset Address
A-1 ((Byte Mode Only)
Low/High Byte Select
Last Low/High Byte Select
A6~A14
tAS
55H
tAH
2AH
55H
Page Address
A15~A18
Page Address
tWC
tBALC
WE
tCP
tCPH
tBAL
CE(1)
tCES
OE
tWHRLP
RY/BY
tDS
tDH
tSRA
DATA
tPHWL
AAH
55H
A0H
Write Data
Last Write Data
SRD
PWD
NOTE: 1.CE is defined as the latter of CE1 or CE2 going low, or the first of CE1 or CE2 going high. 2.Please refer to page 9 for detail page program operation.
P/N: PM0262
REV. 2.0, JAN. 22, 1999
33
INDEX
MX29F8100
ERASE AND PROGRAMMING PERFORMANCE(Note 2)
PARAMETER
Chip/Sector Erase Time
MIN.
LIMITS TYP.
150
MAX. (Note 1)
(Note 2)
UNITS
ms
Page Programming Time
3
(Note 3)
ms
Chip Programming Time
24
75
sec
Erase/Program Cycles
10,000
Cycles
Byte Program Time
24
us
*Note 1: MAX values are all evaluated with polling the status in stead of internal state machine time out. *Note 2: The IC internal state machine is set 2000 ms as maximum chip/sector erase time out. *Note 3: We set 60 ms as production test condition, whereas, the IC internal state machine is set 150 ms as maximum programming time out.
LATCHUP CHARACTERISTICS
MIN. Input Voltage with respect to GND on all pins except I/O pins Input Voltage with respect to GND on all I/O pins Current Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. -1.0V -1.0V -100mA MAX. 13.5V Vcc + 1.0V +100mA
P/N: PM0262
REV. 2.0, JAN. 22, 1999
34
INDEX
MX29F8100
44-PIN PLASTIC SOP
ITEM A B C D E F G H I J K L
NOTE:
MILLIMETERS 28.70 max. 1.10 [REF] 1.27 [TP] .40 .10 [Typ.] .010 min. 3.00 max. 2.80 .13 16.04 .30 12.60 1.72 .15 .10 [Typ.] .80 .20
INCHES 1.130 max. .043 [REF] .050 [TP] .016 .004 [Typ.] .004 min. .118 max. .110 .005 .631 .012 .496
44
23
1 A
22 H I J
G
F K E
.068 .006 .004 [Typ.] .031 .008
D C B L
Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition.
48-PIN PLASTIC TSOP
ITEM A B C D E F G H I J K L M N
NOTE:
MILLIMETERS 20.0 .20 18.40 .10 12.20 max. 0.15 [Typ.] .80 [Typ.] .20 .10 .30 .10 .50 [Typ.] .45 max. 0 ~ .20 1.00 .10 1.27 max. .50 0 ~ 5
INCHES .787 .008 .724 .004 .480 max. .006 [Typ.] .031 [Typ.] .008 .004 .012 .004 .020 [Typ.] .018 max. 0 ~ .008 .039 .004 .050 max. .020 .500
A B
C
N M
K D E F G H I J
L
Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition.
P/N: PM0262
REV. 2.0, JAN. 22, 1999
35
INDEX
MX29F8100
Note. Revision History
Revision No. 1.6 1.7 1.8 1.9 2.0 Description fast access time : 100ns removed fast access time : 100ns Write-Erase cycles change from 1,000/10,000 to 100,000. Erase and Programming Performance table updated Endurance:10K Modify PIN CONFIGURATIONS A19-->A19* Page Date 09/25/1996 06/20/1997 10/29/1997 04/09/1998 01/22/1999
P2
P/N: PM0262
REV. 2.0, JAN. 22, 1999
36
INDEX
MX29F8100
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-8888 FAX:+886-3-578-8887
EUROPE OFFICE:
TEL:+32-2-456-8020 FAX:+32-2-456-8021
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TEL:+81-44-246-9100 FAX:+81-44-246-9105
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TEL:+65-747-2309 FAX:+65-748-4090
TAIPEI OFFICE:
TEL:+886-3-509-3300 FAX:+886-3-509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088 FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900 FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
37

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